Memory segmentation may be utilized for memory management in microprocessors. In general, memory segmentation allows management of the logical address space by providing data and code relocatability and efficient sharing of global resources. For example, in the Intel.RTM. architecture microprocessor, memory is organized into one or more variable length segments, each comprising up to four gigabytes in size. The segmented memory space may be divided into one or more pages. Typically, each segment stores information containing common attributes such as location, size, type (e.g. stack, code or data) and protection characteristics. Memory segmentation in the Intel.RTM. architecture microprocessor provides four levels of protection for isolating and protecting application programs and operating systems from conflict in the address space. The Intel.RTM. architecture microprocessor hardware enforced protection allows the design of systems with a high degree of integrity.
Microprocessors may utilize superscalar execution units to increase performance. In general, a superscalar processor is defined as a processor that contains more than one arithmetic logic unit (ALU). By providing more than one ALU, the processor exhibits the ability to execute instructions in parallel. Although employing a superscalar execution unit potentially provides the capability to execute more than one instruction in parallel, any given sequence of instructions may not be able to take advantage of this capability because the instructions are not independent of one another. Consequently, although a microprocessor may provide the capability to execute more than one instruction concurrently, interrelationships within the sequence of instructions prevents some instructions from being executed concurrently.
A reason that instructions may not be executed concurrently is the existence of conflicts between resource versions. Such conflicts are also known as false dependencies. A false dependency occurs when two instructions in the same sequence use different versions of the same resource at the same time. For example two load instructions, a first instruction in time and a second instruction in time, may use the same segment register to form their respective memory addresses. In this situation, an intervening write to the segment register file may cause the second load instruction to use a different segment register value (version) than the first load instruction. In order to overcome the resource conflict, execution of the second instruction may be delayed until the first instruction no longer uses the resource in contention. Because this delay adversely affects performance, it is desirable to eliminate the false dependencies. Register renaming is a technique that has been used for renaming resources in contention. Conventional register expensive in terms of hardware when applied to renaming segment registers.